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| Solid State Devices, Inc. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: (562) 404-7855 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com SFF25P20S2I series 25 AMP / 200 Volts 125 m P-Channel MOSFET Features: * * * * * * polySi gate cell structure Low ON-resistance UIS (unclamped inductive switching) rated Hermetically Sealed, Isolated Package Low package inductance Stress relief provided by flexible leads - several options available Improved (RDS(ON) QG) figure of merit TX TXV S Level screening available DESIGNER'S DATA SHEET SMD 2 isolated NOTE: SEE DASH# DEFINITION TABLE FOR AVAILABLE LEAD FORMING CONFIGURATION * * Maximum Ratings Drain - Source Voltage Gate - Source Voltage Max. Continuous Drain Current Max. Instantaneous Drain Current (Tj limited) Max. Avalanche current Repetitive Avalanche Energy Total Power Dissipation Operating & Storage Temperature Maximum Thermal Resistance Junction to Case @ TC = 25C @ TC = 25C @ TC = 25C Symbol VDSS VGS ID1 ID3 IAR EAR PD TOP & TSTG R0JC Symbol BVDSS RDS(on) VGS(th) IGSS IDSS Value -200 20 25 95 25 30 250 -55 to +150 0.5 Units V V A A A mJ W C C/W Electrical Characteristics (@25oC, unless otherwise specified) Drain to Source Breakdown Voltage Drain to Source On State Resistance Gate Threshold Voltage Gate to Source Leakage Zero Gate Voltage Drain Current VGS = 0V, ID = 250A VGS = 10V, ID = 12A, Tj= 25oC VGS = 10V, ID = 25A, Tj= 25oC VDS = VGS, ID = 250A VGS = 20V VDS = 160V, VGS = 0V, Tj = 25 C VDS = 160V, VGS = 0V, Tj = 125oC o Min 200 -- -- 3.0 -- -- -- Typ Max -- 110 125 -- -- -- -- -- 120 -- 5.0 100 25 1 Units V m V nA A mA NOTE: All specifications are subject to change without notification. SCD's for these devices should be reviewed by SSDI prior to release. DATA SHEET #: FT0009A DOC Solid State Devices, Inc. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: (562) 404-7855 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com SFF25P20S2I series Symbol gfs Qg Q gs Q gd td(on) tr td(off) tf VSD trr Ciss Coss Crss Electrical Characteristics (@25oC, unless otherwise specified) Forward Transconductance Total Gate Charge Gate to Source Charge Gate to Drain Charge Turn on Delay Time Rise Time Turn off Delay Time Fall Time Diode Forward Voltage Diode Reverse Recovery Time Peak Reverse Recovery Current Reverse Recovery Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance NOTES: Pulse Test: Pulse Width = 300sec, Duty Cycle = 2%. .50 MIN .920 Min 5 -- -- -- -- -- -- -- -- -- -- -- -- Typ Max 12 150 35 70 35 30 70 30 2.0 250 4200 1200 350 -- -- -- -- -- -- -- 3.0 -- -- -- -- Units Mho nC VDS = 10V, ID = 24A, Tj = 25oC VGS = 10V VDS = 100V ID = 12A VGS = 10V VDS = 100V ID = 12A RG = 4.7 IF = 25A, VGS = 0V IF = 24A, di/dt = 100A/usec VGS = 0V VDS = 25V f = 1 MHz nsec V nsec pF .50 MIN 1 .610 2 .290 3 .190 .160 .014 .006 A .160 MAX 3x .11.02 2x .050 .220 .570 .510 .610 TOLERANCES: (UNLESS OTHERWISE SPECIFIED) .XX .02 .XXX .010 880 LEAD FORMING CONFIGURATIONS SMD2I dash# -01 -02 -03 0.062" 0.000" 0.097" A Package SMD2I PIN ASSIGNMENT (Standard) Drain Source Pin 1 Pin 2 Gate Pin 3 |
Price & Availability of SFF25P20S2I
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